DocumentCode :
3093768
Title :
A case study on logic diagnosis for System-on-Chip
Author :
Benabboud, Y. ; Bosio, A. ; Girard, P. ; Pravossoudovitch, S. ; Virazel, A. ; Bouzaida, L. ; Izaute, I.
Author_Institution :
Lab. d´´Inf. de Robot. et de Microelectron. de Montpellier - LIRMM, Univ. Montpellier/CNRS, Montpellier
fYear :
2009
fDate :
16-18 March 2009
Firstpage :
253
Lastpage :
259
Abstract :
This paper presents an industrial case study on logic diagnosis targeting system-on-chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on the effect-cause paradigm. This approach consists of two phases: (i) a fault localization phase resorting to the critical path tracing to determine a set of suspects, (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. To deal with SoC we define a new algebra for the critical path tracing process during fault localization. Experimental results show the diagnosis accuracy, in terms of absolute number of suspects, of the proposed approach. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.
Keywords :
fault location; logic testing; system-on-chip; critical path tracing; effect-cause paradigm; fault localization; fault model allocation phase; logic diagnosis; system-on-chip; Algebra; Circuit faults; Circuit simulation; Electronics industry; Fault diagnosis; Logic functions; Logic gates; Service robots; System-on-a-chip; Testing; Fault Model; Logic Diagnosis; SoC;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2952-3
Electronic_ISBN :
978-1-4244-2953-0
Type :
conf
DOI :
10.1109/ISQED.2009.4810303
Filename :
4810303
Link To Document :
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