DocumentCode :
3093816
Title :
A 14b 200MHz IF-sampling A/D converter with 79.9dB SFDR
Author :
Hakkarainen, V. ; Aho, M. ; Sumanen, L. ; Waltati, M. ; Halonen, K.
Author_Institution :
Electronic Circuit Design Laboratory Helsinki University of Technology, Finland
fYear :
2004
fDate :
8-9 Nov. 2004
Firstpage :
171
Lastpage :
174
Abstract :
This paper presents a 14-bit, 100-MS/s time-interleaved pipeline ADC, which samples input signal from 210-MHz IF-band. Digital self-calibration is employed to compensate gain mismatch and offset between time-interleaved channels as well as mismatches arised from a single ADC channel. A timing skew-insensitive parallel S/H circuit is utilized in order to avoid timing skew between parallel ADC channels. The ADC, fabricated in a 0.35- pm BiCMOS (SiGe) takes an area of 10.2 mm2 reaches an ENOB of 11.4 bits with a 79.9-dB SFDR at 192.5- MHz input and draws 1.4 W from a 3.0-V supply.
Keywords :
Calibration; Circuits; Clocks; Digital signal processing; Error correction; Pipelines; Samarium; Sampling methods; Switches; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Norchip Conference, 2004. Proceedings
Conference_Location :
Oslo, Norway
Print_ISBN :
0-7803-8510-1
Type :
conf
DOI :
10.1109/NORCHP.2004.1423850
Filename :
1423850
Link To Document :
بازگشت