DocumentCode
3093876
Title
A stimulus-free probabilistic model for single-event-upset sensitivity
Author
Rejimon, Thara ; Bhanja, Sanjukta
Author_Institution
South Florida Univ., Tampa, FL, USA
fYear
2006
fDate
3-7 Jan. 2006
Abstract
With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as single-event-upset (SEU), is a growing concern in logic circuits. Accurate understanding and estimation of single-event-upset sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstraction. We propose a probabilistic framework to study the effect of inputs, circuit structure and delay on single-event-upset sensitivity of nodes in logic circuits as a single joint probability distribution function (PDF). To model the effect of timing, we consider signals at their possible arrival times as the random variables of interest. The underlying joint probability distribution function, consists of two components: ideal random variables without the effect of SEU and the random variables affected by the SEU. We use a Bayesian network to represent the joint PDF which is a minimal compact directional graph for efficient probabilistic modeling of uncertainty. The attractive feature of this model is that not only does it use the conditional independence to arrive at a sparse structure, but also utilizes the same for smart probabilistic inference. We show that results with exact (exponential complexity) and approximate non-simulative stimulus-free inference (linear in number of nodes and samples) on benchmark circuits yield accurate estimates in reasonably small computation time.
Keywords
belief networks; integrated circuit design; logic circuits; logic design; radiation hardening (electronics); statistical distributions; Bayesian network; PDF; SEU; benchmark circuits; directional graph; exponential complexity; logic circuits; logic level design abstraction; probability distribution function; single-event-upset sensitivity; smart probabilistic inference; soft error hardening techniques; stimulus-free inference; stimulus-free probabilistic model; Alpha particles; Bayesian methods; Delay effects; Frequency; Logic circuits; Logic design; Logic devices; Probability distribution; Random variables; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2502-4
Type
conf
DOI
10.1109/VLSID.2006.26
Filename
1581439
Link To Document