Title :
A 3Gb/s/wire global on-chip bus with near velocity-of-light latency
Author :
Caputa, Peter ; Svensson, Christer
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
Abstract :
We successfully show the practical feasibility of a purely electrical global on-chip communication link with near velocity-of-light delay. The implemented high-speed link comprises a 5mm long, fully shielded, repeaterless, on-chip global bus reaching 3Gb/s/wire in a standard 0.18μm CMOS process. Transmission-line-style interconnects are achieved by routing signal wires in the thicker top metal M6 layer and utilizing a metal M4 ground return plane to realize near velocity-of-light data transmission. The nominal wire delay is measured to 52.8ps corresponding to 32% of the velocity of light in vacuum. A 22% measured worst-case crosstalk induced delay variation is dominated by inductive coupling.
Keywords :
CMOS integrated circuits; integrated circuit interconnections; system-on-chip; transmission lines; wires; 0.18 micron; 3 Gbit/s; 5 mm; 52.8 ps; CMOS process; crosstalk induced delay variation; global on-chip bus; global on-chip communication link; high-speed link; inductive coupling; metal M4 ground return plane; metal M6 layer; near velocity-of-light delay; near velocity-of-light latency; signal wires; transmission line interconnects; wire delay; Attenuation; CMOS process; Clocks; Delay; Inductance; Integrated circuit interconnections; RF signals; Radio frequency; Repeaters; Wire;
Conference_Titel :
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
Print_ISBN :
0-7695-2502-4
DOI :
10.1109/VLSID.2006.6
