DocumentCode :
3093933
Title :
0.25μ m CMOS analog multiplier for polynomial predistorter
Author :
Nielsen, T.S. ; Lindfors, S. ; Tawfik, S. ; Larsen, T.
Author_Institution :
RISC Division, Center for TeleInFrashucture (CTIF), Aalborg University, Niels Jemes Vej 12, DK-9220, Denmark
fYear :
2004
fDate :
8-9 Nov. 2004
Firstpage :
191
Lastpage :
194
Abstract :
The requirements for a multiplier in a polynomial predistortion circuit are discussed The analog multiplier topology based on sum and difference squaring is found to be suitable, except for some limitations related to interfacing. Two circuit level modifications eliminating the limitations are presented along with experimental results from a multiplier implemented in a 0.25 μ m CMOS technology.
Keywords :
CMOS technology; Circuit topology; Gain; Linearity; MOSFETs; Polynomials; Power amplifiers; Predistortion; Radiofrequency amplifiers; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Norchip Conference, 2004. Proceedings
Conference_Location :
Oslo, Norway
Print_ISBN :
0-7803-8510-1
Type :
conf
DOI :
10.1109/NORCHP.2004.1423855
Filename :
1423855
Link To Document :
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