• DocumentCode
    3093939
  • Title

    A statistical method for fast and accurate capacitance extraction in the presence of floating dummy fills

  • Author

    Batterywala, Shabbir ; Ananthakrishna, Rohit ; Luo, Yansheng ; Gyure, Alex

  • Author_Institution
    ATG, Synopsys Pvt. Ltd., Bangalore, India
  • fYear
    2006
  • fDate
    3-7 Jan. 2006
  • Abstract
    Dummy fills are being extensively used to enhance CMP planarity. However presence of these fills can have a significant impact on the values of interconnect capacitances. Accurate capacitance extraction accounting for these dummies is CPU intensive and cumbersome. For one, there are typically hundreds to thousands of dummy fills in a small layout region, which stress the general purpose capacitance extractor. Second, since these dummy fills are not introduced by the designers, it is of no interest for them to see the capacitances to dummy fills in the extraction reports; they are interested in equivalent capacitances associated with signal power and ground nets. Hence extracting equivalent capacitances across nets of interest in the presence of large number of dummy fills is an important and challenging problem. We present a novel extension to the widely popular Monte-Carlo capacitance extraction technique. Our extension handles the dummy fills efficiently. We demonstrate the accuracy and scalability of our approach by two methods: (i) classical and golden technique of finding equivalent interconnect capacitances by eliminating dummy fills through the network reduction method and (ii) comparing extracted capacitances with measurement data from a test chip.
  • Keywords
    Monte Carlo methods; capacitance measurement; integrated circuit interconnections; integrated circuit testing; statistical analysis; CMP planarity; Monte Carlo method; capacitance extraction technique; floating dummy fills; interconnect capacitances; network reduction method; statistical method; Batteries; Chromium; Conductors; Data mining; Parasitic capacitance; Scalability; Signal design; Space technology; Statistical analysis; Stress;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-2502-4
  • Type

    conf

  • DOI
    10.1109/VLSID.2006.25
  • Filename
    1581443