DocumentCode
3094013
Title
Integrated time counter with 200 ps resolution
Author
Szymanowski, R. ; Kalisz, J.
Author_Institution
Military University of Technology, Kaliskiego 2,00-908 Warsaw, Poland
fYear
2004
fDate
8-9 Nov. 2004
Firstpage
207
Lastpage
210
Abstract
The integrated time counter on a single CMOS FPGA device is presented. A 200 ps resolution has been achieved in the measurement range 0 - I67 ms utilizing two-stage interpolation method. The maximum integral non-linearity of the embedded time-to-digital converters is 312ps. After correction of the linearity error the standard measurement uncertainty below 140ps was obtained. The Delay-Locked Loop (DLL) was used for indirect time stabilization of the delay elements.
Keywords
CMOS technology; Clocks; Counting circuits; Delay lines; Field programmable gate arrays; Interpolation; Linearity; Pulse measurements; Synchronization; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Norchip Conference, 2004. Proceedings
Conference_Location
Oslo, Norway
Print_ISBN
0-7803-8510-1
Type
conf
DOI
10.1109/NORCHP.2004.1423859
Filename
1423859
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