DocumentCode
3094064
Title
Test cost reduction using partitioned grid random access scan
Author
Baik, Dong Hyun ; Saluja, Kewal K.
Author_Institution
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
fYear
2006
fDate
3-7 Jan. 2006
Abstract
The random access scan (RAS) has the ability to address major problems associated with serial-scan method. A practically implementable RAS test architecture called progressive random access scan (PRAS) was introduced earlier. This paper proposes a generalized architecture for the PRAS. We show that the generalized PRAS architecture offers two orders of magnitude gains in test application time over traditional serial scan and is superior to multiple serial scan in terms of the use of tester channels.
Keywords
integrated circuit design; integrated circuit testing; random-access storage; PRAS architecture; RAS test architecture; magnitude gains; partitioned grid random access scan; progressive random access scan; serial-scan method; test cost reduction; Benchmark testing; Circuit testing; Cogeneration; Computer architecture; Costs; Design for testability; Energy consumption; Hardware; Pins; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2502-4
Type
conf
DOI
10.1109/VLSID.2006.157
Filename
1581449
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