DocumentCode
3094111
Title
On methods to improve location based logic diagnosis
Author
Zou, Wei ; Cheng, Wu-Tung ; Reddy, Sudharkar M. ; Tang, Huaxing
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa Univ., USA
fYear
2006
fDate
3-7 Jan. 2006
Abstract
The general flow of location based logic diagnosis begins with finding a set of locations which can explain one or more single location at-a time (SLAT) failing patterns [Bartenstein, 2001], then a heuristic method is used to find subsets of locations which can explain all the SLAT failing patterns are determined as the results of logic diagnosis. However, since the observed test fails may correspond to logic failures from multiple locations, the existing heuristics may find incomplete or wrong locations of the defect due to the ignorance of the correlation between the logic failure locations and the defect. In this work, we first propose several techniques to analyze the relationship of logic failure locations and collapse multiple logic failure locations into single defects, and then use a minimum set covering algorithm to find final diagnosis candidates. In this way, we can not only identify defect type but also improve diagnosis accuracy and resolution. Experimental results on both simulated defects and silicon defects are given to demonstrate effectiveness of the proposed method.
Keywords
failure analysis; fault location; integrated circuit testing; logic testing; silicon; Si; fault diagnosis; location based logic diagnosis; logic failure locations; silicon defects; Algorithm design and analysis; Circuit faults; Circuit simulation; Circuit testing; Failure analysis; Fault diagnosis; Integrated circuit interconnections; Logic devices; Logic testing; Production;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2502-4
Type
conf
DOI
10.1109/VLSID.2006.123
Filename
1581451
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