Accelerating jitter tolerance qualification for high speed serial interfaces

We witness a phenomenal increase in the use of high-speed serial interfaces (HSSIs). Post-silicon validation and testing of HSSIs are critical to guarantee the design quality and the device quality. Jitter tolerance at 10^-12 Bit Error Rate (BER) is a key parameter that is very costly to qualify due to the long test time. This paper considers an acceleration scheme to quantify post-silicon jitter tolerance. It can reduce the test time from hours to seconds in validation and to tens of milliseconds for compliance testing. Experimental results at 3 Gigabit per second (Gbps) data rate demonstrate the accuracy of our technique in pico-second range.