DocumentCode :
3094142
Title :
Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences
Author :
Yoshida, Hiroaki ; Fujita, Masahiro
Author_Institution :
VLSI Design & Educ. Center (VDEC), Univ. of Tokyo, Tokyo
fYear :
2009
fDate :
16-18 March 2009
Firstpage :
366
Lastpage :
370
Abstract :
Rule-based equivalence checking of system-level design descriptions proves the equivalence of two system-level design descriptions by applying the equivalence rules in a bottom-up manner. Since the previous work derives the equivalence of the internal variables based on their names, the method often fails to prove the equivalence when the variable names are changed. This paper proposes a method for improving the accuracy of the rule-based equivalence checking by identifying potential internal equivalences using random simulation. Experimental results using an example design show that the proposed method can prove the equivalence of the designs before and after a practical design optimization.
Keywords :
formal verification; knowledge based systems; software engineering; design optimization; formal verification; rule-based equivalence checking; system-level design descriptions; Costs; Design methodology; Design optimization; Formal verification; Hardware; Large-scale systems; Lead compounds; Software design; System-level design; Very large scale integration; System-level design; formal verification; internal equivalences; random simulation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2952-3
Electronic_ISBN :
978-1-4244-2953-0
Type :
conf
DOI :
10.1109/ISQED.2009.4810322
Filename :
4810322
Link To Document :
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