DocumentCode :
3094219
Title :
A priori formal coverage analysis for protocol properties
Author :
Tiwari, Praveen ; Biswas, Saptarshi ; Mitra, Raj S.
Author_Institution :
Texas Instrum. (India) Pvt. Ltd., Bangalore, India
fYear :
2006
fDate :
3-7 Jan. 2006
Abstract :
Protocol compliance verification is a key component of the overall SOC verification process. Formal techniques have been applied to achieve high confidence in such verification, but the quality of the protocol properties themselves is not subjected to this rigor of verification. Determining the formal coverage of the protocol properties with respect to an implementation is not sufficient, because it may not have captured the full scope of the protocol. We propose a technique to solve this important problem, by formally covering a protocol´s properties independent of the implementation. The coverage is determined with respect to the protocol specification (i.e. its semantics), which is captured as a state transition graph (STG). Developing an STG for a complex protocol is a non-trivial task; in this paper we also propose techniques to efficiently model complex protocol features like pipelining and threading. Results for OCP and AHB are shown to illustrate our approach.
Keywords :
formal specification; formal verification; integrated circuit design; integrated circuit modelling; logic design; protocols; system-on-chip; AHB protocol; OCP protocol; SOC verification process; a priori formal coverage analysis; protocol compliance verification; protocol specification; state transition graph; Formal specifications; Formal verification; Genetic mutations; Hardware; Instruments; Law; Legal factors; Logic; Pipeline processing; Protocols;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-2502-4
Type :
conf
DOI :
10.1109/VLSID.2006.48
Filename :
1581458
Link To Document :
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