DocumentCode
3094244
Title
An integrated approach for combining BDD and SAT provers
Author
Drechsler, Rolf ; Fey, Görschwin ; Kinder, Sebastian
Author_Institution
Inst. of Comput. Sci., Bremen Univ., Germany
fYear
2006
fDate
3-7 Jan. 2006
Abstract
Many formal verification tools today are based on Boolean proof techniques. The two most powerful approaches in this context are binary decision diagrams (BDDs) and methods based on Boolean satisfiability (SAT). Recent studies have shown that BDDs and SAT are orthogonal, i.e. there exist problems where BDDs work well, while SAT solvers fail and vice versa. Beside this, the techniques are very different in general. E.g. SAT solvers try to find a single solution and BDDs represent all solutions in parallel. In this paper the first integrated approach is presented that combines BDDs and SAT within a single data structure. This hybrid approach combines the advantages of the two techniques, i.e. multiple solutions can be computed while the memory requirement remains small. First experimental results demonstrate the quality of the approach in comparison to BDDs and SAT solvers.
Keywords
Boolean functions; binary decision diagrams; computability; formal verification; integrated circuit design; logic design; Boolean proof techniques; Boolean satisfiability; SAT solvers; binary decision diagrams; formal verification tools; Automatic test pattern generation; Binary decision diagrams; Boolean functions; Circuit synthesis; Computer science; Concurrent computing; Data structures; Formal verification;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2502-4
Type
conf
DOI
10.1109/VLSID.2006.44
Filename
1581459
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