A systematic approach to modeling and analysis of transient faults in logic circuits

With technology scaling, the occurrence rate of not only single, but also multiple transients resulting from a single hit is increasing. In this work, we consider the effect of these multiple-event transients on the outputs of logic circuits. Our framework allows for the analysis of soft errors in logic circuits, including several aspects: estimation of the effect of both single and multiple transient faults on both combinational and sequential circuits, analysis of the impact of multiple flip-flop upsets in sequential circuits, and analysis of transient behavior of the soft error rate in the cycles following the hit. The proposed framework can be used to estimate the impact of transient faults stemming not only from radiation, but also other physical phenomena. The results obtained using the proposed framework show that output error rates, resulting from multiple-event transient or multiple-bit upsets can vary across different circuits by several orders of magnitude.