Title :
Heterogeneous floorplanning for FPGAs
Author :
Feng, Yan ; Mehta, Dinesh P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
The large size of modern FPGAs has caused researchers to consider deploying hierarchical techniques in their design. In this paper, we consider the floorplanning of FPGAs. We present a two-step approach for the floorplanning of modern FPGAs that we believe is cleaner and more versatile than recent floorplanners. The steps, based on resource-aware fixed outline simulated annealing and constrained floorplanning, are adapted to address the heterogeneous nature of FPGA floorplanning. Experiments demonstrate the viability of our approach.
Keywords :
field programmable gate arrays; integrated circuit layout; logic design; simulated annealing; FPGA floorplanning; constrained floorplanning; field programmable gate arrays; fixed outline simulated annealing; heterogeneous floorplanning; Application specific integrated circuits; Compaction; Computational modeling; Computer science; Design automation; Field programmable gate arrays; Logic arrays; Logic gates; Scalability; Simulated annealing;
Conference_Titel :
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
Print_ISBN :
0-7695-2502-4
DOI :
10.1109/VLSID.2006.96
