FPGA based real time implementation scheme for ARINC 659 backplane data bus

Integrated Modular Avionics (IMA) architecture provides means for integrating multiple safety-critical applications on a shared hardware in an airborne system. Error free data transfer between different modules of an IMA cabinet is an issue of critical importance. ARINC 659 has proven to be one of the most comprehensive standards for intra-cabinet data transfer within an IMA cabinet of commercial aircrafts. This paper presents a Hardware Descriptive Language (HDL) based modular design and implementation details of the ARINC 659 Line Replaceable Modules (LRM) for backplane data bus communication. LRM consists of two major modules; Bus Interface Unit (BIU) and Host. BIU is used to achieve control functions, state management, synchronization and data transfer on the backplane data bus. Modular approach has been adopted in the design of BIU. Whereas, the functionality of Host is to provide the data to be transferred, monitor BIU activities and ensure error free transmission of the required data through BIU. Altera´s NIOS soft processor core is configured to realize the functionality of the Host. A Direct Memory Access (DMA) interface is used to manage data transfer tasks from Host to Inter Module Memory (IMM) of BIU. The results show that it is highly probable to use FPGA with safety critical soft microprocessor core for practical implementation of the said standard.