New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs

A new word-line driving scheme is proposed in this paper for suppressing oxide-tunneling leakage in sub-65-nm devices. Reducing oxide-tunneling leakage is very essential in sub-65-nm era because of this tunneling leakage component becoming more and more serious comparing with the subthreshold component. In this paper, we propose to raise the word-line-off voltage higher than 0 V thereby relaxing the voltage stress across the oxides. This scheme can reduce not only oxide-tunneling leakage but also switching power because of the swing voltage of the word line being reduced. This scheme has been verified using the 65-nm devices obtained from the Predictive Technology Modeling group. The comparison with the conventional circuit shows the power consumption of the proposed one is lowered by as much as 11%, 19.7%, and 39.9%, at 75degC, 25degC, and -25degC, respectively, when all the rows are in sleep. And, during the read operation, the power consumption including both static and dynamic components is lowered by as much as 8.3%, 10.4%, and 10.9%, at 75degC, 25degC, and -25degC, respectively. At the write operation, amounts of power saving reach 37.5%, 38.7%, and 41.1%, for 75degC, 25degC, and -25degC, respectively, while showing very little delay overhead of word-line driving.