• DocumentCode
    3094509
  • Title

    Bounding supply noise induced path delay variation by a relaxation approach

  • Author

    Wang, Baohua ; Mazumder, Pinaki

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
  • fYear
    2006
  • fDate
    3-7 Jan. 2006
  • Abstract
    This paper presents a general ILP model for analyzing the supply noise induced worst path delay variation. The proposed model can address various modes of supply noise analysis: function based, two-vector pattern based, or multiple cycle analysis, additionally capable of including user-specified constraints. The formulated ILP problem is solved via a relaxation approach, which produces a conservative upper-bound estimation to the worst path delay variation at any iteration. The paper applies sub-gradient optimization to improve those upper bounds. Experimentations have demonstrated the efficiency of the proposed approach, by comparisons with a commercial ILP solver and traditional supply noise modeling approaches.
  • Keywords
    delays; integer programming; integrated circuit design; integrated circuit noise; linear programming; power supply circuits; integer linear programming; path delay variation; relaxation approach; subgradient optimization; supply noise analysis; upper-bound estimation; Delay; Libraries; Logic design; Logic gates; Power grids; Table lookup; Timing; Variable structure systems; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-2502-4
  • Type

    conf

  • DOI
    10.1109/VLSID.2006.53
  • Filename
    1581476