DocumentCode :
3094630
Title :
Lagrangian relaxation based register placement for high-performance circuits
Author :
Chiang, Mei-Fang ; Okamoto, Takumi ; Yoshimura, Takeshi
Author_Institution :
Grad. Sch. of IPS, Waseda Univ., Kitakyushu
fYear :
2009
fDate :
16-18 March 2009
Firstpage :
511
Lastpage :
516
Abstract :
To achieve low-skew clock distribution, clock tree synthesis (CTS) for local clock optimization is used so far. Challenged by the increasing design complexity and performance demand, a new strategy for local clock optimization is used along with register placement for high-performance circuits. Special local clock distribution is used and registers are legalized to fit required skew. In this paper, we study the register placement problem and formulate it as a minimum weighted maximum independent set problem on a weighted conflict graph. Then, we propose a novel Lagrangian relaxation based algorithm. By relaxing the overlap conflict constraints, the problem is transformed into a minimum weighted bipartite matching problem. Experiments show that our method can efficiently place all registers without overlaps with minimized total register movement.
Keywords :
clocks; network synthesis; Lagrangian relaxation; clock tree synthesis; design complexity; high-performance circuits; local clock optimization; low-skew clock distribution; minimum weighted bipartite matching; overlap conflict constraints; register placement; Circuit synthesis; Circuit topology; Clocks; Lagrangian functions; National electric code; Navigation; Pins; Registers; Timing; Uncertainty; Register; clock skew; high-performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2952-3
Electronic_ISBN :
978-1-4244-2953-0
Type :
conf
DOI :
10.1109/ISQED.2009.4810347
Filename :
4810347
Link To Document :
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