Implementation of power managed hyper transport system for transmission of HD video

Hyper transport is a bidirectional, serial/parallel high bandwidth, low latency, point-to-point interface architecture. In this architecture, data can be sent on both rising and falling edges of the clock making it an interface that can transmit the data faster when compared to the other architectures that are available in the market today. This architecture also is ACPI (advanced configuration and power interface) compliant and can provide low power by switching off when there is no activity in the system. This project is aimed to develop a power managed hyper transport system prototype for the transmission of high definition video. Power is managed by switching the system from active state to sleep state when there is no heavy isochronous data flowing and switching it back to the active state before isochronous data arrives, while by-passing the prioritized video data and interrupts. This project is implemented in Verilog and is simulated using ModelSim. From the simulations, it can be observed that at 50% - 70% of isochronous data transfer an overall power saving of 20% - 40% is achieved.