DocumentCode :
3094845
Title :
Retrospective on electronics technology and prospective methods for co-design of IC packaging and manufacturing improvements
Author :
Fjelstad, Joseph
Author_Institution :
Verdant Electron., Cupertino, CA
fYear :
2009
fDate :
16-18 March 2009
Firstpage :
559
Lastpage :
564
Abstract :
The evolution of the electronics manufacturing industry has followed a path laid down by a series of observation and innovations by physicists that have been made practical by electronic interconnection and packaging engineers. With every new discovery, new solutions to take advantage of them and make them practical arose in response. In this manner the technology followed a path akin to the rise of many towns and cities, which were often laid out without any real planning. The results have thus often been less than optimum in terms of traffic flow with twisting roads and odd shaped blocks because of early decisions made without concern for the future. Similarly, today electronic interconnection products are manufactured using a wide range of legacy technologies for design and manufacture that unintentionally conspire create an environment that keeps the industry from creating products that can offer better performance and reliability at lower cost, use less energy and do so in a more environmentally responsible manner. This paper will show how a simple rethinking of the design and manufacturing processes used for electronics and employment of new and alternative co-designed and integrated manufacturing methods could potentially deliver significant untapped potential from future electronics assemblies with little impact on the manufacturing infrastructure.
Keywords :
error statistics; integrated circuit interconnections; integrated circuit manufacture; integrated circuit packaging; IC packaging; bit error rate; chip-to-chip connection; electronics manufacturing industry; electronics technology; interconnection; solder free technology; Cities and towns; Electronics packaging; Industrial electronics; Integrated circuit packaging; Manufacturing processes; Path planning; Pulp manufacturing; Roads; Technological innovation; Technology planning; Occam; Standard grid for design; bit error rate (BER); chip-to-chip connection; co-designed IC package; over the top (OTT) interconnection; solder free technology (SFT); solderless assembly of electronics; ¿The 80% Rule¿;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2952-3
Electronic_ISBN :
978-1-4244-2953-0
Type :
conf
DOI :
10.1109/ISQED.2009.4810355
Filename :
4810355
Link To Document :
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