A high-performance VLSI architecture for advanced encryption standard (AES) algorithm

Author

Kosaraju, Naga M. ; Varanasi, Murali ; Mohanty, Saraju P.

Author_Institution

Comput. Sci. & Eng., South Florida Univ., Tampa, FL, USA

fYear

2006

fDate

3-7 Jan. 2006

Abstract

In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round of the Rijndael algorithm, are generated in real-time by the key-scheduler module by expanding the initial secret key, thus reducing the amount of storage for buffering. Moreover, pipelining is used after each standard round to enhance the throughput. A prototype chip implemented using 0.35 μ CMOS technology resulted in a throughput of 232Mbps for iterative architecture and 1.83Gbps for pipelining architecture.

Keywords

CMOS integrated circuits; VLSI; cryptography; integrated circuit design; 1.83 Gbit/s; 232 Mbit/s; Rijndael algorithm; VLSI architecture; advanced encryption standard algorithm; initial secret key; iterative architecture; key-scheduler module; pipelining architecture; Buffer storage; CMOS technology; Computer architecture; Computer science; Cryptography; Military computing; Pipeline processing; Protection; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on

ISSN

1063-9667

Print_ISBN

0-7695-2502-4

Type

conf

DOI

10.1109/VLSID.2006.9

Filename

1581498