A low-power asymmetric source driver level converter based current-mode signaling scheme for global interconnects

Global interconnects pose a significant challenge to the dense very deep submicron (VDSM) system-on-chips (SoC), due to increasing wire delay and its variations. Hence, interconnection techniques which decrease delay, delay variation and ensure signal integrity, play an important role in future technologies. In this regard, current-mode low-swing interconnection techniques provide an attractive alternative to conventional full-swing voltage-mode techniques in terms of delay, power and noise immunity. In this paper, we present a new current-mode low swing interconnection technique that reduces the delay and delay variations in global interconnects. Simulation results indicate significant savings in power, reduction in delay and increase in noise immunity compared to other techniques.