Title :
Process variation impact on FPGA configuration memory
Author :
Xu, Y.Z. ; Liu, L.S. ; Chan, Mei-Lin ; Watt, J.T.
Author_Institution :
Altera Corp., San Jose, CA
Abstract :
The impact of process local variation on FPGA configuration memory is studied in this paper. Memory cell stability is examined by simulations and experiments on 65 nm and 45 nm processes. A statistical simulation method, which correlates closely with product silicon, has been developed. The results show that the trend of process local variation and memory density scaling adversely impact FPGA configuration memory stability. It is found that the cell stability is greatly affected by cell layout.
Keywords :
SRAM chips; elemental semiconductors; field programmable gate arrays; silicon; FPGA configuration memory; SRAM; Si; memory cell stability; memory density scaling; process variation; silicon; statistical simulation method; Cost function; Design optimization; Field programmable gate arrays; Random access memory; Silicon; Stability; Technological innovation; Temperature; Testing; Threshold voltage; Configuration Memory; FPGA; Process Variation;
Conference_Titel :
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2952-3
Electronic_ISBN :
978-1-4244-2953-0
DOI :
10.1109/ISQED.2009.4810364
