Ultra folded high-speed architectures for Reed Solomon decoders

In this paper, a new high-speed VLSI architecture for decoding Reed-Solomon codes with the Berlekamp-Massey algorithm is presented. The proposed scheme uses the fully folded systolic architecture in which a single array of processors, computes both the error-locator and the error-evaluator polynomials. The proposed scheme utilizes the folding property of systolic array architectures and reduces the number of multipliers and adders drastically at the expense of some compromise in the speed. More interestingly, the proposed architecture requires approximately 60% fewer multipliers and a simpler control structure than the popular RiBM architecture. The reduction in the number of multipliers and adders in the proposed architecture leads to smaller silicon area and lower power consumption.