DocumentCode
3095107
Title
Automatic register banking for low-power clock trees
Author
Hou, Wenting ; Liu, Dick ; Ho, Pei-Hsin
Author_Institution
Synopsys Inc., Mountain View, CA
fYear
2009
fDate
16-18 March 2009
Firstpage
647
Lastpage
652
Abstract
We present an automatic register placement technique that enables the synthesis of low-power clock trees for low-power ICs. On 7 industrial designs, comparing to (1) a commercial base flow and (2) the power-aware placement technique in, the technique respectively reduced clock-tree power by 19.0% and 14.9%, total power by 15.3% and 5.2% and WNS under on-chip variation (plusmn10%) by 1.8% and 1.5% on average.
Keywords
clocks; integrated circuit design; automatic register banking; automatic register placement technique; low-power clock trees; power-aware placement technique; Algorithm design and analysis; Banking; Capacitance; Clocks; Energy consumption; Registers; Switches; Switching frequency; Timing; Wires; clock tree; low-power; register banking;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-2952-3
Electronic_ISBN
978-1-4244-2953-0
Type
conf
DOI
10.1109/ISQED.2009.4810370
Filename
4810370
Link To Document