Title :
Fully-parallel 25 MHz 2.5 Mb CAM
Author :
Schultz, K. ; Shafai, F. ; Gibson, R. ; Bluschke, A. ; Somppi, D.
Author_Institution :
Nortel Semiconductors, Ottawa, Ont., Canada
Abstract :
In a fully-parallel CAM, all stored bits are compared to the search data in one clock cycle. In traditional implementations, the result of a word search is determined by a dynamic NOR of bit comparison results. This leads to two match line transitions per mismatched word per search and excessive power dissipation, since no more than one match is expected. If the dynamic NOR is replaced by a dynamic NAND, transitions occur only on matches, and power savings are realized.
Keywords :
content-addressable storage; 2.5 Mbit; 25 MHz; bit comparison results; clock cycle; dynamic NAND; fully-parallel CAM; match line transitions; power dissipation; power savings; stored bits; word search; CADCAM; Circuits; Clocks; Computer aided manufacturing; Decoding; Degradation; High-speed networks; MOS devices; Read only memory; Wire;
Conference_Titel :
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4344-1
DOI :
10.1109/ISSCC.1998.672497
