DocumentCode :
3095260
Title :
Efficient analog performance macromodeling via sequential design space decomposition
Author :
Ding, Mengmeng ; Vemuri, Ranga
Author_Institution :
Cincinnati Univ., OH, USA
fYear :
2006
fDate :
3-7 Jan. 2006
Abstract :
This paper presents a sequential design space decomposition technique for efficient analog feasibility and performance macromodeling. The performance macromodel is composed of one feasibility classifier and a set of performance regression models. The algorithm sequentially decomposes the design space into smaller partitions. We use a heuristic to identify the regions of significance. Feasibility classifiers of high precision and recall are constructed with low modeling cost within these regions. The final feasibility model is essentially a set of feasibility classifiers, each of which is valid for a subspace of the design space. The performance regression models constructed with much lower training instances have higher accuracy compared to a previous approach.
Keywords :
integrated circuit modelling; logic design; regression analysis; sequential circuits; analog performance macromodeling; feasibility classifier; performance regression models; sequential design space decomposition; Algorithm design and analysis; Circuit simulation; Circuit testing; Computational modeling; Costs; Data acquisition; Force sensors; Humans; Laboratories; Partitioning algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-2502-4
Type :
conf
DOI :
10.1109/VLSID.2006.77
Filename :
1581514
Link To Document :
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