Techniques for on-chip process voltage and temperature detection and compensation

This paper presents techniques to detect process, voltage and temperature (PVT) variations in an integrated circuit chip and wafer. Conventional techniques are limited to detection of process variations in which the MOS devices (NMOS and PMOS) move in similar direction i.e. fast n-fast p or slow n-slow p. The presented techniques can be used to compensate skewed variations on the chip i.e. fast n-slow p or slow n-fast p thus increasing the utilization (yield) of the wafer. The proposed techniques can be implemented in any standard CMOS process and can easily be integrated with any circuit requiring PVT compensation. Major applications of these circuits are in I/O drivers and PVT sensitive analog circuits. For I/O drivers, simulation results show that the rise/fall time variation with PVT has been reduced to more than half using the proposed circuits.