DocumentCode
3095430
Title
Using level restoring method for dual supply voltage
Author
Sadeghi, K. ; Emadi, M. ; Farbiz, F.
Author_Institution
VLSI Lab, Sharif Univ. of Technol., Tehran, Iran
fYear
2006
fDate
3-7 Jan. 2006
Abstract
A new level converter for use in dual voltage SOI digital circuits is presented. This technique uses the idea of keeper transistors, and consumes less power compared to the traditional methods. The effects of load capacitance on the circuit are studied by extensive simulations.
Keywords
digital integrated circuits; integrated circuit design; low-power electronics; silicon-on-insulator; transistors; SOI digital circuits; dual supply voltage; keeper transistors; level converter; level restoring method; load capacitance; Capacitance; Circuit simulation; Clustering algorithms; Delay; Digital circuits; Dynamic voltage scaling; Energy consumption; Low voltage; Threshold voltage; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2502-4
Type
conf
DOI
10.1109/VLSID.2006.165
Filename
1581522
Link To Document