PVT variation impact on voltage island formation in MPSoC design

On-chip process, voltage, and temperature (PVT) variations are projected to be a major bottleneck in deep submicron design. Such variations can change performance characteristics and push power budgets beyond their limits. In a voltage/frequency island (VFI) design, the initial VFI´s determined using optimization without considering PVT may not be suitable after fabrication. This can lead to degradation in energy that largely offsets the advantage of using VFI. Thus, it is crucial to include PVT variations in any prefabrication energy optimization algorithm to improve the post-fabricaiton design quality. In this paper, we present a methodology that can reduce the differences by including PVT variations in the optimization. We analyze the PVT impact for different PVT characteristics and propose ways to handle the issue with a penalty of only 3%.