DocumentCode :
30956
Title :
Modeling and High-Frequency Simulation of InAs Nanowires
Author :
Popescu, Bogdan ; Popescu, Dan ; Lugli, Paolo
Author_Institution :
Inst. for Nanoelectron., Tech. Univ. Munich, Munich, Germany
Volume :
13
Issue :
4
fYear :
2014
fDate :
Jul-14
Firstpage :
850
Lastpage :
856
Abstract :
In this paper, we have investigated the transport in InAs nanowire-based wrap gate field-effect transistors and their high-frequency performance. State-of-the-art InAs devices reveal excellent dc performance in terms of transconductance, subthreshold slope, and saturation behavior. Only, very recently high-frequency measurements have been performed on these devices, demonstrating that they can operate well in the gigahertz range. However, their intrinsic high-frequency performance and the limiting mechanism in reaching the optimal limit have not been fully understood yet. One of the main reasons lies in the technological difficulties in contacting the nanometer devices and in the parasitic elements that arise from this imperfect measurement setup. Making use of a sophisticated hydrodynamic simulator, we are able to successfully reproduce the experimental output characteristics over the entire measurement range. Next, we also perform a detailed simulation study of the frequency response for the measured samples, with and without an extrinsic parasitic network. Based on our simulations, we deduce that the intrinsic high-frequency performance of these devices is at least one order of magnitude higher than currently reached today, in terms of maximum oscillation frequency and cutoff frequency, and that the parasitic network is the major limiting factor. Furthermore, we identify the parasitic elements that have the greatest impact on the device performance and we explain their working principles.
Keywords :
III-V semiconductors; field effect transistors; indium compounds; nanowires; InAs; cutoff frequency; dc performance; extrinsic parasitic network; frequency response; high frequency simulation; hydrodynamic simulator; maximum oscillation frequency; nanometer devices; nanowires; saturation behavior; subthreshold slope; transconductance; wrap gate field effect transistors; Capacitance; Cutoff frequency; Frequency measurement; Logic gates; Mathematical model; Nanowires; Transistors; Cutoff frequency; InAs; field-effect transistor (FET); nanowire (NW); simulation; trap states; wrap gate;
fLanguage :
English
Journal_Title :
Nanotechnology, IEEE Transactions on
Publisher :
ieee
ISSN :
1536-125X
Type :
jour
DOI :
10.1109/TNANO.2014.2328435
Filename :
6824202
Link To Document :
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