Area & power efficient VLSI architecture for computing pseudo inverse of channel matrix in a MIMO wireless system

Weight and size are the bottlenecks of portable wireless systems which are in turn dependent on area and power consumption of electronic systems. The situation becomes even worse if wireless systems are equipped with multiple input and multiple output (MIMO) technology which involves highly complex signal processing. This paper proposes an area and power efficient VLSI architecture for computing the pseudo inverse of augmented channel matrix used in MIMO systems. Results indicate 25% area and 24% power reduction compared to previous architecture in the literature without degrading the BER performance.