DocumentCode :
3095837
Title :
An Evaluation of the Sieving Device YASD for 1024-Bit Integers
Author :
Hirota, Naoyuki ; Izu, Tetsuya ; Kunihiro, Noboru ; Ohta, Kazuo
Author_Institution :
Univ. of Electro-Commun., Chofu, Japan
fYear :
2010
fDate :
14-16 Sept. 2010
Firstpage :
546
Lastpage :
551
Abstract :
Geiselmann and Steinwandt proposed an ASIC based hardware design “YASD” for the sieving step in the number field sieve (NFS) method of integer factorization in 2004. The design is attractive since its regular structure seems suitable for implementation, however, performance valuation for 1024-bit integers has not been provided. This paper firstly evaluates the performance of YASD for 1024-bit integers by a simple extrapolation under the same assumptions of the original YASD. In our estimation, optimized YASD for 1024-bit integers requires 42200 mm2 and about 10600 years for the sieving. Since we did not consider the wiring problem and the mini-factoring problem, even if YASD for 1024-bit integers are manufactured, further circuit area and time will be required.
Keywords :
application specific integrated circuits; digital arithmetic; extrapolation; integrated circuit design; number theory; 1024-bit integer; ASIC- based hardware design; YASD; extrapolation; integer factorization; number field sieve method; performance evaluation; sieving device; yet another sieving device; Clocks; Estimation; Polynomials; Random access memory; Registers; Routing; Transistors; 1024-bit; Hardware; Integer Factorization; RSA;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Network-Based Information Systems (NBiS), 2010 13th International Conference on
Conference_Location :
Takayama
ISSN :
2157-0418
Print_ISBN :
978-1-4244-8053-1
Electronic_ISBN :
2157-0418
Type :
conf
DOI :
10.1109/NBiS.2010.61
Filename :
5636266
Link To Document :
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