Title :
Semi-custom design of adiabatic adder circuits
Author :
Bhaaskaran, V. S Kanchana ; Salivahanan, S. ; Emmanuel, D.S.
Author_Institution :
SSN Coll. of Eng., Chennai, India
Abstract :
The paper presents the design, evaluation and performance comparison of cell based, low power adiabatic adder circuits operated by two-phase sinusoidal power clock signals, as against the literatures providing the operation of various adiabatic circuits, focusing on inverter circuits and logic gates, powered by ramp, three phase and four phase clock signals. The cells are designed for the quasi-adiabatic families, namely, 2N2P, 2N2N2P, PFAL, ADSL and IPGL for configuring complex adder circuits. A family of adiabatic cell based designs for carry lookahead adders and tree adders were designed. The simulations prove that the cell based design of tree adder circuits can save energy ranging from 2 to 100 over a frequency range of operation of 2MHz to 200MHz against the static CMOS circuit implementation. The schematic edit and T-Spice of Tanner tools formed the simulation environment.
Keywords :
CMOS logic circuits; adders; invertors; logic design; logic gates; low-power electronics; 2 to 200 MHz; T-Spice; Tanner tools; adiabatic adder circuits; carry lookahead adders; inverter circuits; logic gates; quasi-adiabatic families; sinusoidal power clock signals; static CMOS circuit; tree adders; Adders; Circuit simulation; Clocks; Film bulk acoustic resonators; Frequency; Logic circuits; Switches; Switching circuits; Very large scale integration; Voltage;
Conference_Titel :
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
Print_ISBN :
0-7695-2502-4
DOI :
10.1109/VLSID.2006.144