• DocumentCode
    3096037
  • Title

    Aliasing analysis of spectral statistical response compaction techniques

  • Author

    Khan, Omar I. ; Bushnell, Michael L.

  • Author_Institution
    Dept. of Electr. & Comput. Eng.,, Rutgers Univ., Piscataway, NJ, USA
  • fYear
    2006
  • fDate
    3-7 Jan. 2006
  • Abstract
    We present aliasing models for statistical response compacters (SRCs) for built-in self-testing (BIST) (Khan and Bushnell, 2004). The SRCs are drastically different from the conventional multiple-input signature register (MISR), and use the signal processing Hadamard transform to extract the digital spectral content in output bit streams of circuits and store it in counters. Any deviation of the spectral content from the good machine spectral content indicates a fault. We use the asymmetric error model (AEM) (Xavier et al., 1992) to describe the behavior of a response compacter for a faulty circuit-under-test (CUT). We construct Markov processes for the aliasing models of the response compacters, which have never been studied. The Markov processes iteratively compute exact aliasing probabilities for any test session length and determine the asymptotic probability of aliasing for statistical response compactor 1 (SRC1). Other compacters (SRC2 and SRC5) have too many Markov process states and formulating exact aliasing probability equations is infeasible. So, we present only the asymptotic aliasing probability results, which converge to very low values rapidly. SRC1 does not alias at all on the ISCAS ´89 benchmarks, but SRC2 and 5 alias occasionally. The model agrees with previously published simulations (Khan and Bushnell, 2004).
  • Keywords
    Hadamard transforms; Markov processes; built-in self test; signal processing; spectral analysis; statistical analysis; Markov process; Markov processes; aliasing analysis; aliasing probabilities; asymmetric error model; asymptotic probability; built-in self-testing; digital spectral content; faulty circuit-under-test; multiple-input signature register; signal processing Hadamard transform; spectral statistical response compaction; statistical response compacters; test session length; Built-in self-test; Circuit faults; Circuit testing; Compaction; Counting circuits; Digital signal processing; Markov processes; Probability; Registers; Spectral analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-2502-4
  • Type

    conf

  • DOI
    10.1109/VLSID.2006.33
  • Filename
    1581558