Testing high-speed IO links using on-die circuitry

This paper describes a novel technique to enable characterization of high-speed IO links and transceivers without the use of special external test equipment. The test circuit has been implemented in 7-metal 90nm CMOS technology. A register file has been used to characterize a high-speed IO link by recording information such as the number of errors, the time of the error and to calibrate the transceiver circuit parameters. The testing approach uses the IEEE 1149.1 JTAG protocol to feed the control signals and to capture the status of key nodes in the transceivers. The high-speed register file operating at 625 MHz has been made seamlessly readable through the JTAG scan chain operating at a maximum of 80 MHz. The simulation results show that we can successfully test the system and capture the behavior of the transceiver and link.