Analog macromodeling for combined resistive vias, resistive bridges, and capacitive crosstalk delay faults

The single stuck-at fault model is ineffective in detecting non-traditional resistive via, resistive bridge, and capacitive crosstalk coupling faults that cause timing failures in high-frequency digital circuits. We propose a new combined resistive via, resistive bridging, and capacitive coupling fault model. We use an analog macromodel of the fault to generate tests with a multiple delay, simulation-based, sequential path-delay fault digital fault simulator for automatic test-pattern generation (ATPG). The focus of this paper is the analog macromodels, whereas a companion paper (Chary and Bushnell, 2006) gives the ATPG method. We characterize the delay due to the via resistance and R and C couplings at the fault site, with many variations, using analog simulation and store this in the precomputed macromodel. The macromodel supplies the extra line delay resulting from the fault during ATPG, which eliminates analog simulation during fault simulation. Unlike Breuer (Chen et al., 2002), we use simulation-based sequential ATPG, rather than PODEM, with this macromodel to obtain more latitude and accuracy for complex fault models for deep submicron (DSM) circuits. We present the various validated analog macromodels for a 0.25 μm TSMC MOSIS process.