A low-jitter multiphase digital delay-locked loop for nuclear instruments and biomedical imaging applications

This paper presents a novel digital delay-locked loop (DDLL) dedicated to generate multiphase delayed clocks for the development of the multi-channel analog-to-digital converters (ADCs) and/or time-to-digital converters (TDCs). The DDLL consists of a digital delay chain using linear delay elements, a Bangbang phase detector, a Up/Down counter and a digital filter. The digital filter is utilized to reduce digital ripples when DDLL is locked. A prototype chip of the proposed DDLL with 32 delay cells is designed and fabricated in AMS 0.35 μm CMOS process. The die area is 690 μm × 73 μm. For the DDLL core, the rms jitter and the peak-to-peak jitter of is 0 and 19.8 ps at 50 MHz clock. However, jitter-tolerant performances can be achieved when the DDLL core and the digital filter are used as a multiphase clock generator. The total power dissipation is about 3 mW.