DocumentCode :
3096085
Title :
An on-chip diagnosis methodology for embedded cores with replaceable modules
Author :
Tekumalla, Ramesh C.
Author_Institution :
ATI Res., Inc., Marlborough, MA, USA
fYear :
2006
fDate :
3-7 Jan. 2006
Abstract :
We propose a design for test and diagnosis architecture that simplifies the process of identifying failures within a failing sub-module, without explicitly identifying the faults responsible for that failure. The extra hardware eliminates the post-processing step needed to process the failure logs from the tester and automatically determines the sub-modules inside a core that must be replaced. The proposed methodology reduces the turnaround time for locating a failing module or sub-module and also facilitates testing and diagnosis at the same time. Experimental results are presented using industrial test-cases to validate the effectiveness of the proposed method.
Keywords :
design for testability; fault simulation; integrated circuit testing; design for test; diagnosis architecture; embedded cores; failing sub-module; failure logs; on-chip diagnosis methodology; replaceable modules; Automatic testing; Bandwidth; Circuit faults; Circuit testing; Combinational circuits; Compaction; Design methodology; Fault diagnosis; Hardware; Pins;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-2502-4
Type :
conf
DOI :
10.1109/VLSID.2006.45
Filename :
1581562
Link To Document :
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