HCI lifetime enhancement by double implanted S/D (DISD) of Nch MOSFET in 0.25 μm CMOS technology

Author

Wu, David ; Luning, Scott ; Ju, DH ; Kepler, Nick

Author_Institution

Logic Technol. Dev. Dept., Adv. Micro Devices Inc., Sunnyvale, CA, USA

fYear

1997

fDate

13-16 Oct 1997

Firstpage

45

Lastpage

46

Abstract

The results of an intensive study of drain engineering work to improve the hot carrier injection (HCI) reliability of N-channel MOSFETs in 0.25 μm CMOS technology are presented. While an As/P LDD structure improved HCI by sacrificing off-current, an alternative method of integrating phosphorus into the heavy dose As S/D junction delivers an equivalent HCI lifetime and an even lower off-current. Around one order of magnitude of HCI lifetime enhancement has been achieved with this P-doping of the S/D. Device simulations supported our approach

Keywords

CMOS integrated circuits; MOSFET; doping profiles; hot carriers; integrated circuit reliability; ion implantation; 0.25 micron; As/P LDD structure; CMOS technology; HCI lifetime; HCI lifetime enhancement; N-channel MOSFETs; Nch MOSFET; P-doping; Si; SiO₂-Si:As,P; device simulations; double implanted S/D; drain engineering; heavy dose As S/D junction; hot carrier injection reliability; off-current; phosphorus integration; Application specific processors; CMOS logic circuits; CMOS technology; DH-HEMTs; Human computer interaction; Implants; Logic devices; MOSFET circuits; Oxidation; Reliability engineering;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 1997 IEEE International

Conference_Location

Lake Tahoe, CA

Print_ISBN

0-7803-4205-4

Type

conf

DOI

10.1109/IRWS.1997.660280

Filename

660280