A flexible model for evaluating the behavior of hardware/software systems

Hardware-software co-design is becoming a “must” for many embedded applications requiring to tradeoff a number of constraints such as size, cost, performance, real-time requirements, design flexibility, etc. Even if, according to the purpose of the digital system, the range of possible architectures is rather wide, for our field of interest (telecom embedded systems) the target architecture can be roughly described as composed of a microprocessor surrounded by some hardware modules connected through buses. The aim of this paper is to present a model (and the related CAD environment) supporting the simultaneous analysis of functionality, timing performance (in terms of execution time of hw and sw modules and bus use), and execution profile of the system specification assuming the given target architecture. The goal of the proposed approach has been to define a simulation algorithm able to consider the partition of each section of the specification and the consequent bus traffic at the system level, in order to enable the designer to efficiently debug and evaluate the specification while considering the timing issues of a mixed hw-sw architecture very close to the final one. The paper gives also the flavor of the CAD environment built around the presented simulation strategy