Title :
Practice on layout-level radiation hardened technologies for I/O cells
Author :
Wang Jing ; Zuocheng, Xing ; Ping, Huang ; Tianran, Wang ; Guitao, Fu
Author_Institution :
Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
Abstract :
Radiation hardened technologies are important to improve the anti-radiation performance of ICs. In this paper, several I/O cells in 0.18μm CMOS process are designed and radiation hardening technologies through layout design are researched. The function, timing and the effect of the ESD protection scheme for the I/O cells are analyzed by HSPICE simulation. The way of layout-level radiation hardening consists of single event effect and total ionizing dose effect. TCAD simulation is used to analyze the validity of the technologies adopted in the paper, and the experimental results indicate that the single event latch-up threshold increases effectively, and the anti-radiation performance is improved.
Keywords :
CMOS integrated circuits; SPICE; electrostatic discharge; integrated circuit layout; radiation hardening (electronics); semiconductor device models; semiconductor process modelling; technology CAD (electronics); timing circuits; CMOS process; ESD protection; HSPICE simulation; I/O cells; TCAD simulation; antiradiation performance; circuit timing; input-output circuits; layout design; layout-level radiation hardened technology; radiation hardening technology; single event effect; single event latch-up threshold; size 0.18 mum; total ionizing dose effect; CMOS integrated circuits; Heating; Integrated circuit modeling; Petroleum; Radiation hardening; Semiconductor device modeling; Silicon; ESD; I/O cells; Radiation Hardened; Single Event Effect; Single Event Latch-up; TCAD; Total Ionizing Dose;
Conference_Titel :
Information Networking and Automation (ICINA), 2010 International Conference on
Conference_Location :
Kunming
Print_ISBN :
978-1-4244-8104-0
Electronic_ISBN :
978-1-4244-8106-4
DOI :
10.1109/ICINA.2010.5636369
