Title :
A 128 Mb early prototype for gigascale single-electron memories
Author :
Yano, K. ; Ishii, T. ; Sane, T. ; Mine, T. ; Murai, F. ; Kure, T. ; Seki, K.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
A 128Mb single-electron memory targets minimum-bit-cost technology. The cell has a double stacked structure, in which two cells are integrated in an ideal contact area, 4F/sup 2/. The cell-to-cell characteristics variations, the main difficulty in large scale integration, are compensated with the dummy-cell-referenced verified read/write.
Keywords :
single electron transistors; 128 Mbit; cell-to-cell characteristics; double stacked structure; dummy-cell-referenced verified read/write; gigascale single-electron memories; ideal contact area; large scale integration; minimum-bit-cost technology; Circuits; Design engineering; Flash memory; Laboratories; Large scale integration; Optical wavelength conversion; Prototypes; Random access memory; Single electron memory; Stochastic processes;
Conference_Titel :
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4344-1
DOI :
10.1109/ISSCC.1998.672509
