Title :
An improved voltage-controlled delay line for delay locked loops
Author :
Luo, Gang ; Zeng, Xianjun
Author_Institution :
Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha, China
Abstract :
This paper presents a new voltage controlled delay line (VCDL) for a 30-phase 500MHz DLL. The new VCDL circuit solves the problem of flicker noise caused by the tail current source. The post-simulation result indicates that the VCDL has moderate linearity range, low Processing-Voltage-Temperature (PVT) sensitivity and good noise resistance. It can be perfectly applied in the 5Gbps Over-sampling based Clock and Data Recovery (CDR) circuit.
Keywords :
active networks; circuit noise; clock and data recovery circuits; delay lines; delay lock loops; flicker noise; 30 phase 500 MHz DLL; bit rate 5 Gbit/s; clock and data recovery circuit; delay locked loop; flicker noise problem; frequency 500 MHz; noise resistance; processing voltage temperature sensitivity; tail current source; voltage controlled delay line; Delay; Phase noise; Resistance; Switching circuits; Synchronization; Transistors; Clock and Data Recovery circuit; delay-locked loop; phase noise; voltage controlled delay line;
Conference_Titel :
Computer Research and Development (ICCRD), 2011 3rd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-61284-839-6
DOI :
10.1109/ICCRD.2011.5764122
