Analytical modeling and simulation for dual metal symmetrical gate stack (DMGAS) cylindrical/surrounded gate MOSFET

Author

Ghosh, Pujarini ; Haldar, Subhasis ; Gupta, R.S. ; Gupta, Mridula

Author_Institution

Dept. of Electron. Sci., Univ. of Delhi, New Delhi, India

fYear

2011

fDate

7-9 Dec. 2011

Firstpage

1

Lastpage

2

Abstract

The advancement of CMOS technology has enabled the Si based industry to meet the technological requirements according to the market needs. Rapid advancement and steady downscaling of device dimensions establish these requirements. Miniaturization of MOSFET leads to short channel effects (SCE) and a reduction in current drivability. Various architectures are proposed to overcome the scaling limitations. Among this cylindrical /surrounded (CGT/SGT) gate MOSFET offers a high packing density, steep subthreshold characteristics and higher current drive. This structure has a large effective channel and the gate surrounds the silicon pillar results in high packing density and increased SCE immunity.

Keywords

CMOS integrated circuits; MOSFET; semiconductor device models; CMOS technology; SCE immunity; dual metal symmetrical gate stack cylindrical-surrounded gate MOSFET; short channel effects; silicon based industry; steep subthreshold characteristics; Analytical models; Dielectrics; Educational institutions; Logic gates; MOSFET circuits; Metals; Three dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium (ISDRS), 2011 International

Conference_Location

College Park, MD

Print_ISBN

978-1-4577-1755-0

Type

conf

DOI

10.1109/ISDRS.2011.6135152

Filename

6135152