MorphoSys: a reconfigurable architecture for multimedia applications

Author

Singh, Hartej ; Lee, Ming-Hau ; Lu, Guangming ; Kurdahi, Fadi J. ; Bagherzadeh, Nader ; Filho, Eliseu M C

Author_Institution

California Univ., Irvine, CA, USA

fYear

1998

fDate

30 Sep-3 Oct 1998

Firstpage

134

Lastpage

139

Abstract

We describe the MorphoSys reconfigurable system, which combines a reconfigurable array of processor cells with a RISC processor core and a high bandwidth memory interface unit. We introduce the array architecture, its configuration memory, inter-connection network, role of the control processor and related components. Architecture implementation is described in brief and the efficacy of MorphoSys is demonstrated through simulation of video compression (MPEG-2) and target-recognition applications. Comparison with other implementations illustrates that MorphoSys achieves higher performance by up to 10X

Keywords

data compression; multimedia computing; multiprocessor interconnection networks; parallel architectures; reconfigurable architectures; reduced instruction set computing; video coding; MorphoSys; RISC processor core; array architecture; configuration memory; control processor; high bandwidth memory interface unit; inter-connection network; multimedia applications; processor cells; reconfigurable architecture; target-recognition applications; video compression; Application software; Bandwidth; Computer architecture; Delay estimation; Field programmable gate arrays; Hardware; Reconfigurable architectures; Reduced instruction set computing; Streaming media; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on

Conference_Location

Rio de Janeiro

Print_ISBN

0-8186-8704-5

Type

conf

DOI

10.1109/SBCCI.1998.715427

Filename

715427