Title :
A low-power, compact size millimeter-wave two-stage current-reused low noise amplifier in 90-nm CMOS technology
Author :
Hung-Ting Chou ; Zhi-Lin Ke ; Hwann-Kaeo Chiou
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Abstract :
This paper presents a millimeter-wave (MMW) two-stage low noise amplifier (LNA) that adopts a current-reused topology to reduce the power consumption. The designed current-reused LNA comprises two stacked common source (CS) amplifiers with the same dc current for each stage to enhance the power gain. The proposed LNA is fabricated in tsmcTM 90-nm RF CMOS technology that achieves a peak S21 gain of 12 dB, a noise figure (NF) of 6.9 dB, an input third-intercept point (IIP3) of -4.1 dBm at 51 GHz under DC power of 7.7 mW from a 1.4 V supply voltage. The proposed LNA with transmission line (TL) inductors yields a compact chip size of only 0.37 mm2 and thus the calculated figure-of-merit (FoM) is up to 5.24 at 51 GHz.
Keywords :
CMOS integrated circuits; inductors; low noise amplifiers; millimetre wave amplifiers; power consumption; transmission lines; RF CMOS technology; common source amplifiers; compact size millimeter-wave two-stage current-reused low noise amplifier; current-reused topology to; figure-of-merit; frequency 5.24 GHz to 51 GHz; input third-intercept point; millimeter-wave; power 7.7 mW; power consumption; power gain; size 90 nm; transmission line inductors; two-stage low noise amplifier; voltage 1.4 V; CMOS integrated circuits; CMOS process; Gain; Noise measurement; Power demand; Topology; current-reused topology; low power LNA; millimeter-wave (MMW);
Conference_Titel :
Microwave Conference Proceedings (APMC), 2012 Asia-Pacific
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4577-1330-9
Electronic_ISBN :
978-1-4577-1331-6
DOI :
10.1109/APMC.2012.6421723