Topological parameters for library free technology mapping

This paper presents a methodology for library free technology mapping. This task is the technology mapping targeting virtual libraries available through cell generators. The proposed methodology was implemented in a tool called TABA-Transistor Assignment with BDDs representing complex gates. The tool is able to translate a set of Boolean equations into a net list of CMOS complex gates implementing the initial description at the transistor level. As the cells from a virtual library are generated on-the-fly, results are presented in terms of topological parameters due to the absence of pre-characterization. The main contributions of this paper are the introduction of topological parameters and the investigation of the evolution of these parameters with the size of the virtual libraries