Self-aligned multi-channel silicon nanowire field-effect transistors

Recently, semiconductor nanowire and nanotube field-effect transistors (FETs) have been intensively studied as fundamental building blocks for three-dimensional circuit technologies. Si nanowire FETs with multiple nanowire channels are very attractive as they may have higher performance compared with single nanowire transistors. However, techniques for the assembly of Si nanowire FETs remain a barrier to the development of devices with better performance. Fabrication approaches for current research are mostly based on harvesting and positioning the as-synthesized semiconductor nanowires with methods such as fluidic alignment, dielectrophoresis, or nano-scale probe methods. These methods undoubtedly introduce contaminants surrounding the multi-nanowire channel. This contamination will adversely influence the device interface state density (D_it) and degrade the device performance.